1. Field of the Invention
The present invention generally refers to a semiconductor structure, and particularly to a semiconductor structure comprising a source region, a lateral diffused channel region as well as a drain region where a field plate is disposed on the drain end.
2. Description of Prior Art
In the prior art, semiconductor structures with lateral channel regions are known, such as LDMOS transistors (LDMOS=Lateral Diffused Metal Oxide Semiconductor). Such LDMOS transistors comprise a long drain region on the drain end, also referred to as LDD (LDD=Lightly Doped Drain). It is the disadvantage of such structures that an increased impact ionisation occurs in the area of the connection of the LDD to the drain contact implantation with higher drain voltages and drain currents. The electron-hole pairs generated that way cause an additional current not flowing through the channel of the transistor. This additional current, which is not flowing through the channel of the transistor, is undesirable and is to be avoided.
One solution to this problem, as it is known from the prior art, is to provide an additional implantation region between the lightly doped drain and the drain implantation, wherein a doping concentration of the additional implantation region lies between a doping concentration of the lightly doped drain region and the drain implantation. Thereby the concentration gradient is decreased, which reduces the impact ionisation.
With reference to FIG. 9, a known LDMOS transistor according to the prior art is discussed in more detail. The semiconductor structure in FIG. 9 is in its totality provided with reference number 100 and comprises a substrate 102 of p-material, in which the structures of the LDMOS transistor are generated.
A source region 104 with a high n+-doping is formed in the substrate 102. A source contact 106 made from a metal connected with the source connection S is disposed on the source region 104. Further, a drain region 108 with a high n+-doping is formed in the substrate 102. A drain contact 110 is disposed on the drain region and connected to a drain connection D. A gate oxide 112 is disposed on the substrate 102, and a gate contact 114 out of metal connected to a gate connection G is disposed thereon. Below the gate oxide 112 the channel region 116 of the LDMOS transistor structure is fixed. Between the channel region 116 and the drain region 108 a lightly doped drain region (LDD) 118 with a low n−-doping is formed. Between the lightly doped drain region 118 and the drain region 108 an intermediate region with an n-doping is formed, which lies between the n+-doping of drain region 108 and the n−-doping of the lightly doped drain region 118. The arrangement of the intermediate region 120 leads to a reduction of the doping concentration gradient, whereby an impact ionisation in the region of the actual drain implantation, the drain region 108, is reduced. Arrangements as described with reference to FIG. 9 are for example known from U.S. Pat. No. 4,172,260 and U.S. Pat. No. 6,020,611.
In FIG. 10, a voltage distribution between the gate region and the drain region of the LDMOS transistor from FIG. 9 is illustrated schematically. In the example shown in FIG. 10, a voltage Ugate of 16 V is applied to gate connection G, and a drain voltage Udrain of 26 V is applied to the drain connection D. In a first region A, mainly extending in the substrate region 102 to below the gate region 114 and the source region 104, the potential lies at about −0.55 V. In region B, adjacent to region A, the potential lies between about 6.224 V and about 13 V. In region C, extending starting from a region below the drain region 108 across the edge areas of the intermediate region 102 and the LDD 118 across the regions 118 and 120, the voltage lies in the range between about 13 V to about 20 V. In region D, comprising the drain region 108 as well as a region above it and the largest part of the intermediate region 120 as well as the region above, the voltage lies in the range between about 20 V to about 26 V.
From FIG. 10, the range of the raised voltage above the drain region 108 and the intermediate region 120 as well as in the border region of the two areas can be seen. Due to the high gradient of electrical potential predominating there, a significant impact ionisation generating a corresponding current still occurs, despite the achieved reduction of the doping concentration gradient.